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Size reduction techniques for vital compliant VHDL simulation models

United States Patent

7,085,701
August 1, 2006
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.
Rich; Marvin J. (Poughkeepsie, NY), Misra; Ashutosh (Bangalore, IN)
International Business Machines Corporation (Armonk, NY)
10/ 038,311
20030125917
January 2, 2002
This invention was made with government support under subcontract B338307 under prime contract W-7405-ENG-48 awarded by the Department of Energy. The Government has certain rights in this invention.