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Redundant single event upset supression system

United States Patent

April 4, 2006
View the Complete Patent at the US Patent & Trademark Office
Fermi National Accelerator Laboratory - Visit the Office of Research and Technology Applications Website
CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.
Hoff; James R. (Wheaton, IL)
Universities Research Association, Inc. (Washington, DC)
10/ 735,489
December 12, 2003
GOVERNMENT INTEREST The United States Federal Government has right to this invention pursuant to Contract No. DE-AC02-76CH03000 between Universities Research Corporation and the United States Department of Energy.