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Buffered coscheduling for parallel programming and enhanced fault tolerance

United States Patent

January 31, 2006
View the Complete Patent at the US Patent & Trademark Office
Los Alamos National Laboratory - Visit the Technology Transfer Division Website
A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors
Petrini; Fabrizio (Los Alamos, NM), Feng; Wu-chun (Los Alamos, NM)
The Regents of the University of California (Los Alamos, NM)
09/ 895,570
June 28, 2001
STATEMENT REGARDING FEDERAL RIGHTS This invention was made with government support under Contract No. W-7405-ENG-36 awarded by the U.S. Department of Energy. The government has certain rights in the invention.