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Method and system for selecting data sampling phase for self timed interface logic

United States Patent

6,839,861
January 4, 2005
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.
Hoke; Joseph Michael (Millerton, NY), Ferraiolo; Frank D. (Essex, VT), Lo; Tin-Chee (Fishkill, NY), Yarolin; John Michael (Williston, VT)
International Business Machines Corporation (Armonk, NY)
09/ 918,081
20030023891
July 30, 2001
GOVERNMENT RIGHTS This invention was made with Government support under subcontract B338307 under prime contract W-7405-ENG-48 awarded by the Department of Energy. The Government has certain rights in this invention.