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Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

United States Patent

6,624,493
September 23, 2003
View the Complete Patent at the US Patent & Trademark Office
Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.
Welch; James D. (Omaha, NE)
09/ 716,046
November 20, 2000
The invention in this application was conceived and developed in part under support provided by a grant from the Energy Related Inventions Program of the United States Federal Department of Energy, Contract No. DE-FG47-93R701314. The United States Government has certain rights in this invention.