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Bit error rate tester using fast parallel generation of linear recurring sequences

United States Patent

May 6, 2003
View the Complete Patent at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
A fast method for generating linear recurring sequences by parallel linear recurring sequence generators (LRSGs) with a feedback circuit optimized to balance minimum propagation delay against maximal sequence period. Parallel generation of linear recurring sequences requires decimating the sequence (creating small contiguous sections of the sequence in each LRSG). A companion matrix form is selected depending on whether the LFSR is right-shifting or left-shifting. The companion matrix is completed by selecting a primitive irreducible polynomial with 1's most closely grouped in a corner of the companion matrix. A decimation matrix is created by raising the companion matrix to the (n*k) power, where k is the number of parallel LRSGs and n is the number of bits to be generated at a time by each LRSG. Companion matrices with 1's closely grouped in a corner will yield sparse decimation matrices. A feedback circuit comprised of XOR logic gates implements the decimation matrix in hardware. Sparse decimation matrices can be implemented with minimum number of XOR gates, and therefore a minimum propagation delay through the feedback circuit. The LRSG of the invention is particularly well suited to use as a bit error rate tester on high speed communication lines because it permits the receiver to synchronize to the transmitted pattern within 2n bits.
Pierson; Lyndon G. (Albuquerque, NM), Witzke; Edward L. (Edgewood, NM), Maestas; Joseph H. (Bosque Farms, NM)
Sandia Corporation (Albuquerque, NM)
09/ 426,073
October 21, 1999
The U.S. Government has rights in this invention as provided for by the terms of DE-AC04-94AL85000 awarded by the Department of Energy.