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Coatings on reflective mask substrates

United States Patent

March 5, 2002
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A process for creating a mask substrate involving depositing: 1) a coating on one or both sides of a low thermal expansion material EUVL mask substrate to improve defect inspection, surface finishing, and defect levels; and 2) a high dielectric coating, on the backside to facilitate electrostatic chucking and to correct for any bowing caused by the stress imbalance imparted by either other deposited coatings or the multilayer coating of the mask substrate. An film, such as TaSi, may be deposited on the front side and/or back of the low thermal expansion material before the material coating to balance the stress. The low thermal expansion material with a silicon overlayer and a silicon and/or other conductive underlayer enables improved defect inspection and stress balancing.
Tong; William Man-Wai (Oakland, CA), Taylor; John S. (Livermore, CA), Hector; Scott D. (Oakland, CA), Mangat; Pawitter J. S. (Gilbert, AZ), Stivers; Alan R. (San Jose, CA), Kofron; Patrick G. (San Jose, CA), Thompson; Matthew A. (Austin, TX)
The Regents of the University of California (Oakland, CA)
09/ 587,836
June 6, 2000
The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California for the operation of Lawrence Livermore National Laboratory.