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L-connect routing of die surface pads to the die edge for stacking in a 3D array

United States Patent

6,034,438
March 7, 2000
View the Complete Patent at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.
Petersen; Robert W. (Dublin, CA)
The Regents of the University of California (Oakland, CA)
08/ 733,854
October 18, 1996
The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the United States Department of Energy and the University of California for the operation of Lawrence Livermore National Laboratory.