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WAFER LEVEL INTERCONNECTION AND METHOD

United States Patent Application

20090256254
A1
View the Complete Application at the US Patent & Trademark Office
National Renewable Energy Laboratory - Visit the NREL Technology Transfer Website
A semiconductor assembly includes a semiconductor wafer including backside contact pads coupled to respective contact regions of different signal types and insulation separating the backside contact regions by signal type. The semiconductor assembly further includes metallization situated over at least a portion of the insulation and interconnecting the backside contact pads.
Burdick, JR., William Edward (Niskayuna, NY), Erlbaum, Jeffrey Scott (Albany, NY), Nagarkar, Kaustubh Ravindra (Guilderland, NY), Tonapi, Sandeep Shrikant (Chandler, AZ)
GENERAL ELECTRIC COMPANY (Schenectady NY)
12/ 100,447
April 10, 2008
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH & DEVELOPMENT [0001] This invention was made with Government support under contract number DE-AC36-99GO10337 awarded by the United States Department of Energy. The Government has certain rights in the invention.