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THERMAL MANAGEMENT OF ON-CHIP CACHES THROUGH POWER DENSITY MINIMIZATION

United States Patent Application

20080120514
A1
View the Complete Application at the US Patent & Trademark Office
Certain embodiments provide systems and methods for reducing power consumption in on-chip caches. Certain embodiments include Power Density-Minimized Architecture (PMA) and Block Permutation Scheme (BPS) for thermal management of on-chip caches. Instead of turning off entire banks, PMA architecture spreads out active parts in a cache bank by turning off alternating rows in a bank. This reduces the power density of the active parts in the cache, which then lowers the junction temperature. The drop in the temperature results in energy savings from the remaining active parts of the cache. BPS aims to maximize the physical distance between the logically consecutive blocks of the cache. Since there is spatial locality in caches, this distribution results in an increase in the distance between hot spots, thereby reducing the peak temperature. The drop in the peak temperature then results in a leakage power reduction in the cache.
Ismail, Yehea (Morton Grove, IL), Memik, Gokhan (Evanston, IL), Ku, Ja Chun (Seoul, KR), Ozdemir, Serkan (Evanston, IL)
11/ 938,040
November 9, 2007
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] This invention was made with government support under Grant No. CCF-0541337 awarded by the National Science Foundation (NSF), Grant No. DE-FG02-05ER25691 awarded by the Department of Energy (DoE), and Northwestern Cufs Nos. 0830-350-J205 and 0680-350-FF02. The government has certain rights in the invention.