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LOW ENERGY CONSUMPTION MANTISSA MULTIPLICATION FOR FLOATING POINT MULTIPLY-ADD OPERATIONS

United States Patent Application

20180095728
A1
View the Complete Application at the US Patent & Trademark Office
A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.
Hasenplaugh, William C. (Boston, MA), Fleming, JR., Kermin E. (Hudson, MA), Fossum, Tryggve (Northborough, MA), Steely, JR., Simon C. (Hudson, NH)
Intel Corporation (Santa Clara CA)
15/ 283,295
October 1, 2016
STATEMENT OF GOVERNMENT INTEREST [0001] This invention was made with Government support under contract number 7216501 awarded by the Department of Energy. The Government has certain rights in this invention.