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METHOD AND APPARATUS FOR REDUCING MEMORY ACCESS LATENCY

United States Patent Application

20180081563
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.
Roberts, David A. (Sunnyvale, CA)
15/ 272,894
September 22, 2016
GOVERNMENT LICENSE RIGHTS [0001] This invention was made with government support under Prime Contract Number DE-AC52-07NA27344, Subcontract No. B608045 awarded by the Department of Energy (DOE). The government has certain rights in the invention.