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LIGHT-WEIGHT CACHE COHERENCE FOR DATA PROCESSORS WITH LIMITED DATA SHARING

United States Patent Application

20180074958
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.
Jayasena, Nuwan (Sunnyvale, CA), Boyer, Michael (Bellevue, WA)
Advanced Micro Devices, Inc. (Sunnyvale CA)
15/ 264,804
September 14, 2016
STATEMENT REGARDING GOVERNMENT SPONSORED RESEARCH [0001] This invention was made with Government support under Prime Contract Number DE-AC52-07NA27344, Subcontract No. B609201 awarded by the Department of Energy (DOE). The Government has certain rights in this invention.