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DYNAMIC WRITE LATENCY FOR MEMORY CONTROLLER USING DATA PATTERN EXTRACTION

United States Patent Application

20180018104
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
Methods and apparatus of dynamically determining a variable reset latency time based on a data pattern of the data to be written into memory is disclosed. A memory controller determines a variable reset latency time for a plurality of memory cells depending on the bit values to be written into the plurality of memory cells in response to a write request having corresponding bit values. A write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells. The memory controller writes the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.
Farahani, Amin Farmahini (Sunnyvale, CA), Cho, Benjamin Y. (Sunnyvale, CA), Jayasena, Nuwan (Sunnyvale, CA)
15/ 211,488
July 15, 2016
GOVERNMENT LICENSE RIGHTS [0001] This invention was made with government support under Prime Contract Number DE-AC52-07NA27344, Subcontract No. B608045 awarded by the Department of Energy (DOE). The government has certain rights in the invention.