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SYSTEM AND METHOD FOR PROTECTING GPU MEMORY INSTRUCTIONS AGAINST FAULTS

United States Patent Application

20170371743
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.
Kalamatianos, John (Boxborough, MA), Mantor, Michael (Orlando, FL), Gurumurthi, Sudhanva (Austin, TX)
Advanced Micro Devices, Inc. (Sunnyvale CA)
15/ 190,015
June 22, 2016
GOVERNMENT RIGHTS [0001] This invention was made with Government support under (Prime Contract No. DE-AC52-07NA27344, Subcontract No. B600716) awarded by Department of Energy (DOE). The Government has certain rights in this invention.