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MEMORY CONTROLLER THAT FORCES PREFETCHES IN RESPONSE TO A PRESENT ROW ADDRESS CHANGE TIMING CONSTRAINT

United States Patent Application

20170371791
A1
View the Complete Application at the US Patent & Trademark Office
An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.
RANJAN, Ashish (West Lafayette, IN), KOZHIKKOTTU, Vivek (Hillsboro, OR)
15/ 195,887
June 28, 2016
STATEMENT OF GOVERNMENT RIGHTS [0001] This invention was made with Government support under contract number 8608115 awarded by the Department of Energy. The Government has certain rights in the invention.