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THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES

United States Patent Application

20170200820
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.
Conway, Adam (Livermore, CA), Harrison, Sara Elizabeth (Fremont, CA), Nikolic, Rebecca (Oakland, CA), Shao, Qinghui (Fremont, CA), Voss, Lars (Livermore, CA)
14/ 990,612
January 7, 2016
[0001] The United States Government has rights in this invention pursuant to Contract No. DE-AC52-07NA27344 between the United States Department of Energy and Lawrence Livermore National Security, LLC for the operation of Lawrence Livermore National Laboratory.