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IN-MEMORY INTERCONNECT PROTOCOL CONFIGURATION REGISTERS

United States Patent Application

20170123987
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.
Cheng, Kevin Y. (Austin, TX), Roberts, David A. (Santa Cruz, CA)
14/ 928,981
October 30, 2015
[0001] The invention described herein was made with government support under contract number DE-AC52-07NA27344, Subcontract No. B608045 awarded by the United States Department of Energy. The United States Government has certain rights in the invention.