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INTERCONNECT ARCHITECTURE FOR THREE-DIMENSIONAL PROCESSING SYSTEMS

United States Patent Application

20170139635
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
Jayasena, Nuwan S. (Sunnyvale, CA), Eckert, Yasuko (Bellevue, WA)
14/ 944,099
November 17, 2015
GOVERNMENT LICENSE RIGHTS [0001] This invention was made with Government support under Prime Contract Number DE-AC52-07NA27344, Subcontract Number B609201 awarded by the National Nuclear Security Agency (NNSA), a division of the Department of Energy (DOE). The Government has certain rights in this invention.