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FAST PROCESS FLOW, ON-WAFER INTERCONNECTION AND SINGULATION FOR MEPV

United States Patent Application

20170162724
A1
View the Complete Application at the US Patent & Trademark Office
Sandia National Laboratories - Visit the Intellectual Property Management and Licensing Website
A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.
Okandan, Murat (Edgewood, NM), Nielson, Gregory N. (Lehi, UT), Cruz-Campa, Jose Luis (Waltham, MA), Sanchez, Carlos Anthony (Belen, NM)
15/ 360,553
November 23, 2016
STATEMENT OF GOVERNMENT RIGHTS [0002] This invention was developed under Contract DE-AC04-94AL85000 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.