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LOGICAL MEMORY ADDRESS REGIONS

United States Patent Application

20170046272
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.
Farmahini-Farahani, Amin (Santa Clara, CA), Roberts, David A. (Cambridge, MA)
15/ 133,033
April 19, 2016
BACKGROUND [0002] The invention described herein was made with government support under contract number DE-AC52-07NA27344 awarded by the United States Department of Energy. The United States Government has certain rights in the invention.