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MULTIPLE CORE COMPUTER PROCESSOR WITH GLOBALLY-ACCESSIBLE LOCAL MEMORIES

United States Patent Application

20160371226
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Berkeley National Laboratory - Visit the Technology Transfer and Intellectual Property Management Department Website
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
Shalf, John (Oakland, CA), Donofrio, David (San Francisco, CA), Oliker, Leonid (San Francisco, CA)
15/ 243,634
August 22, 2016
STATEMENT OF GOVERNMENT SUPPORT [0002] This invention was made with government support under Contract No. DE-ACO2-05CH11231 awarded by the U.S. Department of Energy. The government has certain rights in this invention.