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METHOD AND APPARATUS FOR SELECTIVE AND POWER-AWARE MEMORY ERROR PROTECTION AND MEMORY MANAGEMENT

United States Patent Application

20160301428
A1
View the Complete Application at the US Patent & Trademark Office
A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.
Andrade Costa, Carlos H. (White Plains, NY), Cher, Chen-Yong (Port Chester, NY), Park, Yoonho (Chappaqua, NY), Rosenburg, Bryan S. (Cortlandt Manor, NY), Ryu, Kyung D. (New City, NY)
14/ 684,368
April 11, 2015
STATEMENT OF GOVERNMENT RIGHTS [0001] This invention was made with Government support under Contract No. B599858 awarded by the Department of Energy. The Government has certain rights in this invention.