A processor includes a transistor pair of a first transistor and a second transistor. The first transistor of the transistor pair is coupled to a Spaser and configured to output a drive current to the Spaser to pump the Spaser. Responsive to the drive current, the Spaser outputs surface plasmon polaritons (SPPs) which are fed to a plasmonic interconnect wire. The plasmonic interconnect wire propagates the SPPs. Further, the SPPs propagated on the plasmonic interconnect wire are detected by a phototransistor. Responsive to detecting the SPPs, the phototransistor generates an output current that is fed to a gate terminal of the second transistor to charge the second transistor.
STATEMENT OF GOVERNMENT LICENSE RIGHTS
 The U.S. Government may have certain rights in this invention, as provided for by the terms of Grants No. DE-FG02-01ER15213 and No. DE-FG02-11ER46789 awarded by the U.S. Department of Energy.