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METHOD TO FABRICATE QUANTUM DOT FIELD-EFFECT TRANSISTORS WITHOUT BIAS-STRESS EFFECT

United States Patent Application

20160181407
A1
View the Complete Application at the US Patent & Trademark Office
Disclosed herein are embodiments of a method to form quantum dot field-effect transistors (QD FETs) having little to no bias-stress effect. Bias-stress effect can be reduced or eliminated through, as an example, the use of a gas or liquid to remove ligands and/or reduce charge trapping on the QD FETs, followed by deposition of an inorganic or organic matrix around the QDs in the FET.
Law, Matt (Irvine, CA), Tolentino, Jason (Irvine, CA)
14/ 973,522
December 17, 2015
STATEMENT REGARDING FEDERALLY SPONSORED R&D [0001] The present disclosure was developed, at least in part, with government support under Grant Nos. DE-SC0003904, awarded by the Department of Energy as well as the Graduate Research Fellowship, awarded by the National Science Foundation. The United States Government may have rights to this disclosure.