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Method and structure for high-performance linear algebra in the presence of limited outstanding miss slots

United States Patent Application

20060168401
A1
View the Complete Application at the US Patent & Trademark Office
A method and structure of increasing computational efficiency in a computer that comprises at least one processing unit, a first memory device servicing the at least one processing unit, and at least one other memory device servicing the at least one processing unit. The first memory device has a memory line larger than an increment of data consumed by the at least one processing unit and has a pre-set number of allowable outstanding data misses before the processing unit is stalled. In a data retrieval responding to an allowable outstanding data miss, at least one additional data is included in a line of data retrieved from the at least one other memory device. The additional data comprises data that will prevent the pre-set number of outstanding data misses from being reached, reduce the chance that the pre-set number of outstanding data misses will be reached, or delay the time at which the pre-set number of outstanding data misses is reached.
Chatterjee, Siddhartha (Yorktown Heights, NY), Gunnels, John A. (Brewster, NY), Bachega, Leonardo R. (West Lafayette, IN)
International Business Machines Corporation (Armonk NY)
11/ 041,935
January 26, 2005
U.S. GOVERNMENT RIGHTS IN THE INVENTION [0003] This invention was made with Government support under Contract No. Blue Gene/L B517552 awarded by the Department of Energy. The Government has certain rights in this invention.