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ERROR DETECTION AND CORRECTION UTILIZING LOCALLY STORED PARITY INFORMATION

United States Patent Application

20160117221
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A processing system includes a memory coupled to a processor device. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor device has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.
Nair, Prashant Jayaprakash (Atlanta, GA), Roberts, David A. (Santa Cruz, CA)
14/ 521,183
October 22, 2014
GOVERNMENT LICENSE RIGHTS [0001] This invention was made with Government support under Prime Contract Number DE-AC52-07NA27344, Subcontract Number B600716 awarded by the Department of Energy (DOE). The Government has certain rights in this invention.