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United States Patent Application

View the Complete Application at the US Patent & Trademark Office
A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
Gara, Alan (Palo Alto, CA), Chen, Dong (Croton on Hudson, NY), Heidelberger, Philip (Cortlandt Manor, NY), Ohmacht, Martin (Yorktown Heigths, NY)
14/ 973,021
December 17, 2015
GOVERNMENT RIGHTS [0003] This invention was made with Government support under Contract No.: B554331, awarded by Department of Energy. The Government has certain rights to this invention.