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HETEROGENEOUS FUNCTION UNIT DISPATCH IN A GRAPHICS PROCESSING UNIT

United States Patent Application

20160085551
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.
Greathouse, Joseph L. (Austin, TX), Meswani, Mitesh R. (Austin, TX), Puthoor, Sooraj (Austin, TX), Yudanov, Dmitri (Austin, TX), O'Connor, James M. (Austin, TX)
ADVANCED MICRO DEVICES, INC. (Sunnyvale CA)
14/ 490,213
September 18, 2014
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0001] This invention was made with government support under Prime Contract Number DE-AC52-07NA27344, Subcontract Number B600716 awarded by the Department of Energy (DOE). The government has certain rights in the invention.