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ADDRESS-PARTITIONED MULTI-CLASS PHYSICAL MEMORY SYSTEM

United States Patent Application

20150261662
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Livermore National Laboratory - Visit the Industrial Partnerships Office Website
A multilevel memory system includes a plurality of memories and a processor having a memory controller. The memory controller classifies each memory in accordance with a plurality of memory classes based on its level, its type, or both. The memory controller partitions a unified memory address space into contiguous address blocks and allocates the address blocks among the memory classes. In some implementations, the memory controller then can partition the address blocks assigned to each given memory class into address subblocks and interleave the address subblocks among the memories of the memory class.
LOH, Gabriel H. (Bellevue, WA), JAYASENA, Nuwan S. (Sunnyvale, CA), IGNATOWSKI, Michael (Austin, TX)
ADVANCED MICRO DEVICES, INC. (SUNNYVALE CA)
14/ 206,512
March 12, 2014
GOVERNMENT LICENSE RIGHTS [0001] This invention was made with government support under Prime Contract Number DE-AC52-07NA27344, Subcontract Number B600716 awarded by the Department of Energy (DOE). The Government has certain rights in this invention.