Skip to Content
Find More Like This
Return to Search

MULTIPLE-CORE COMPUTER PROCESSOR FOR REVERSE TIME MIGRATION

United States Patent Application

20140310467
A1
View the Complete Application at the US Patent & Trademark Office
Lawrence Berkeley National Laboratory - Visit the Technology Transfer and Intellectual Property Management Department Website
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.
Shalf, John (Oakland, CA), Donofrio, David (San Francisco, CA), Oliker, Leonid (San Francisco, CA), Kruger, Jens (Ravensburg, DE), Williams, Samuel (San Ramon, CA)
14/ 354,502
October 26, 2012
STATEMENT OF GOVERNMENT SUPPORT [0002] This invention was made with government support under Contract No. DE-AC02-05CH11231 awarded by the U.S. Department of Energy. The government has certain rights in this invention.