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United States Patent Application

View the Complete Application at the US Patent & Trademark Office
Lawrence Berkeley National Laboratory - Visit the Technology Transfer and Intellectual Property Management Department Website
This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.
Michelogiannakis, Georgios (Berkeley, CA), Shalf, John (Oakland, CA)
The Regents of the University of California (Oakland CA)
14/ 250,085
April 10, 2014
STATEMENT OF GOVERNMENT SUPPORT [0002] This invention was made with government support under Contract No. DE-AC02-05CH11231 awarded by the U.S. Department of Energy. The government has certain rights in this invention.