Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage using the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.
STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH
 This invention was made with government support under Grant No. DE-EE0002892 awarded by the U.S. Department of Energy and Grant No. ECCS-0903466 awarded by the National Science Foundation. The government has certain rights in the invention.