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United States Patent Application

View the Complete Application at the US Patent & Trademark Office
A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
Coteus, Paul W. (Yorktown, NY), Hall, Shawn A. (Pleasantville, NY), Takken, Todd E. (Brewster, NY)
14/ 699,988
April 29, 2015
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] This invention was made with Government support under Contract No. B601996 awarded by the United States Department of Energy. The Government has certain rights in this invention.