Skip to Content
Find More Like This
Return to Search

VERTICAL INTEGRATED SILICON NANOWIRE FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATION

United States Patent Application

20110233512
A1
View the Complete Application at the US Patent & Trademark Office
Vertical integrated field effect transistor circuits and methods are described which are fabricated from Silicon, Germanium, or a combination Silicon and Germanium based on nanowires grown in place on the substrate. By way of example, vertical integrated transistors are formed from one or more nanowires which have been insulated, had a gate deposited thereon, and to which a drain is coupled to the exposed tips of one or more of the nanowires. The nanowires are preferably grown over a surface or according to a desired pattern in response to dispersing metal nanoclusters over the desired portions of the substrate. In one preferred implementation, SiCl.sub.4 is utilized as a gas phase precursor during the nanowire growth process. In place nanowire growth is also taught in conjunction with structures, such as trenches, while bridging forms of nanowires are also described.
Yang, Peidong (El Cerrito, CA), Goldberger, Joshua (Chicago, IL), Hochbaum, Allon (Berkeley, CA), Fan, Rong (Pasadena, CA), He, Rongrui (Albany, CA)
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (Oakland CA)
12/ 015,044
January 16, 2008
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0003] This invention was made with Government support under Grant No. DE-FG02-02ER46021, awarded by the Department of Energy. The Government has certain rights in this invention.