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Digital-data receiver synchronization

United States Patent Application

*** PATENT GRANTED ***
20040105516
6,925,135
A1
View the Complete Application at the US Patent & Trademark Office
An improved digital-data receiver synchronization apparatus and method is provided wherein memory devices in the receiver such as phase-lock loops are provided with composite phase-frequency detectors, mutually cross-connected comparison feedback means, or both to provide robust reception of digital data signals. The apparatus and method are preferrably utilized with synchronous architecture wherein a single master clock is used to provide frequency signals to the memory devices, and also can be used with asynchronous architecture. The apparatus and method provide fast lock-up times in moderately to severely noisy conditions and have improved tolerances to clock asymmetries.
Smith, Stephen F. (Loudon, TN), Turner, Gary W. (Clinton, TN)
10/ 722,274
November 25, 2003
[0001] This invention was made with United States Government support awarded by the United States Department of Energy under contract to UT-Battelle, LLC. The United States has certain rights to this invention.